Ilia Ovsiannikov, Ph.D.      ilya at ovsy dot com,

Linked In, Patents, Publications, Google Scholar

Location: San Jose, CA or Los Angeles, CA

Summary

- Hands-on product, technology development veteran leader focusing on deep learning accelerator hardware, imaging sensors including 3D, LiDAR and color. - Architected a Samsung's neural inference hardware accelerator for smartphones. - In a previous life designed SoC imaging sensors, designed into top smart phones brands, 1B+ sensors sold. - Vast breadth of experience in hardware, software: ASIC, deep learning, imaging, cloud, full-stack, mobile software, robotics. 66+ granted patents.

Confidential at Confidential, 4/2020-now

• • Technology, product development

Samsung Semiconductor Inc., San Jose, CA & Pasadena CA, 12/2008- 4/2020. Vice President

Head of Samsung Semiconductor Advanced Systems Lab. Formerly director, chief architect.

• • Architected, with small team, Samsung 2nd generation deep learning neural inferencing accelerator for smartphones, self-driving cars

  • Lab delivered multiple world-first generations of advanced technology for deep learning, machine learning, see publications

    • Neural inference accelerator hardware architecture for mobile devices, smart-phones, self-driving cars, future IoT devices

    • Deep learning neural network model optimization for execution on hardware accelerator

    • Applications of deep learning for mobile, automotive (ADAS)

  • Lab delivered multiple generations of world-class technology for CMOS image sensors, see publications

    • Architecture, design of experimental CMOS imaging sensors for mobile, automotive applications

      • Automotive solid-state LiDAR

      • 3D structured light sensors, cameras for mobile devices

      • 3D time-of-flight sensors

      • RGBZ (color-and-depth) single-chip time-of-flight sensors

      • DVS (dynamic vision sensor)

      • Stacked, multi-layer sensors

    • Image processing for above-mentioned sensors. E.g. full pipelines for 3D, color (demosaic, denoise, color correction, etc.), super-resolution, etc.

    • Delivered prototype cameras, applications for above-mentioned sensors

    • Imaging sensor characterization and image quality evaluation (e.g. ISP-processed)

MagnaChip Semiconductor, Inc., Sunnyvale CA, 2008. VP of Imaging Solutions

• • Delivered as VP and lead design and R&D of CMOS SOC image sensors including digital design, ISP algorithm development, firmware development, physical implementation, verification and systems engineering. Team successfully taped out 1.3Mpix, 2MPix, 3MPix and VGA sensor/SOC products, designed next-generation 3M, 5M, VGA.

Micron Imaging, Pasadena CA, 2005-2008. R&D manager and architect. (previously Aptina, now On Semiconductor)

• • Delivered as lead for firmware and hardware engineers a line of imaging SOC products; project management and architecture

  • Delivered as lead critical function-wide design, research and development of a wide variety of camera processing functions for series of new products – demosaic, noise reduction, defect correction, sharpening, tonal correction, preferred color reproduction, flare cancellation, auto-exposure, auto-focus, tonal correction, anti-shake, fill flash, channel balancing, tuning and others. Delivered verified hardware-ready solutions for subsequent implementation.

Related products: SoC imager mt9s311 [press release], mt9t111d00stc, mt9p111 [press release]

Arecont Vision, Alta Dena CA, 2005. Vice President of Engineering

• • Accomplished IP cameras designs - high-resolution high-speed IP cameras, day and day/night operation. Productized designs including design for yield, FCC, CE, safety. Completed FCC/CE/safety training.

Micron Imaging, Pasadena CA, 2002-2005. Senior system architect, design lead, project and group manager. [Now On Semiconductor]

• • Delivered 2M SOC project, a very-high volume OEM camera-on-a-chip built into mobile camera phones – architected, managed, developed and designed next generation camera-on-chip, comprising complete processing from raw Bayer to JPEG. Developed, specified architecture and/or directed design of all modules, including interpolation/demosaic, noise reduction, defect correction, lens shading compensation, sRGB color correction, gamma correction, decimator, FIFOs, auto-exposure, white balance, auto-focus, flicker avoidance, camera control, flash, sensor control and other features. Architected and designed from ground-up control subsystem and firmware. Led calibration, tuning, debug and support; led mask revs. Directed floor-planning, timing closure, specified memories, designed clock logic, interfaced color pipeline to sensor. Performed functional team management, project scheduling, interfacing, process development, recruiting. Completed Cadence project management training,

Related Product: mt9d111d00stc SoC imager

• • Delivered VGA SOC, a very-high volume OEM camera-on-a-chip used in camera phones – the first part that made Micron Technology take off; architected, developed, designed the part and managed the design, development and implementation group. Directed/architected lens shading, designed pipeline logic, architected and designed decimator. Led mixed-signal debug to production quality part, secured design wins with industry-leading mobile phone manufacturers, provided priority customer support, trouble-shooting, calibration, prototyping, settings, tuning. Pipe-cleaned first part into manufacturing (1st high-volume imaging part in the company), including test and yield issues; managed, led and/or implemented metal mask revs.

Related Product: mt9v111d00stc SoC imager

• • Delivered VGA SOC project – implemented digital backend and managed group. Carried out synthesis, PAR and gate-netlist simulations. Led mixed-signal debug, secured design wins and provided/led customer support

  • Delivered NTSC SOC design, JPEG core optimization, JPEG reorder buffer architecture, asynchronous MCU bus interface design, re-design sensor core for high dynamic range operation. Prototyped designs in FPGA.

ModelSim, Ambit PKS, Silicon Ensemble suite, DFII, Synopsys, Formality, Fastscan, Assura, Hercules, Nanosim, Synplify Pro, Leonardo Spectrum, Xilinx ISE. VHDL and Verilog. C, assembler, VB, Matlab, Delphi, Perl, c-shell.

More products associated with the above mentioned development efforts:

SoC imager mt9d112d00stc, mt9m111d00stc, mt9m112d00stc, mt9m113d00stc, mt9v112d00stc, mt9v113d00stc [press release]

Rockwell Scientific, Camarillo (CA), 2000-2002. Research scientist

• • Accomplished CMOS imaging sensor digital and mixed-signal design; designed digital timing block w/black level logic, readout registers

  • Accomplished test chip design, top-level LVS/DRC

  • Delivered board-level camera design, image processing system design, imaging sensor characterization and camera software development.

DFII, Synopsys, Verilog, LVS/DRC, Spectre, Virtuoso, PAR, embedded memory, Dracula (edited rule stacks), Calibre, Assura, HSPICE (edited models), OrCAD, Xilinx and Lattice FPGA/CPLD, Board-level low-noise design, packaging, probe testing, C++ Builder, Delphi, COM/COM+

Photobit, Pasadena (CA), 1999-2000. Research scientist

• • Delivered characterization, experimental simulations and product CMOS imagers as member of image sensor development and characterization group. Developed a full range of software and hardware for image acquisition, analysis, digital still camera image processing. In-depth understanding of all aspects, such as color processing algorithms, VLSI, software/hardware and optics. Co-authored a DoD and 3 NASA SBIR reports.

MS Visual C++, C++ Builder, Delphi, Matlab, Xilinx, VHDL, MicroSim/PSPICE, HSPICE, DSP assembly

Xerox, El Segundo, 1998. Intern in infrastructure service R&D

• • Software development using Java/JDK

University of Southern California, 1995-1999. Research Assistant, project lead.

• • Delivered Annotator Project as author, team lead, a state-of-the-art system for on-line annotations. Won a two-year grant from Fuji-Xerox Palo Alto Xerox Research Labs. Four publications.

Java/JDK, Informix & Illustra DBMS, datablades, C++

Miscellaneous Skills & Experience

Algorithms, Deep Learning, Machine Learning

• • Deep neural networks hands-on, object recognition; familiar with RNN, GAN, reinforcement learning, most other architectures

  • Classical machine learning, statistical learning, classification, regression, boosting, bagging, naive Bayes, Bayesian networks (course), trees, clustering, rules, support vector machine, restricted Boltzmann machine.

  • Visual recognition: feature extraction (e.g. SIFT/SURF), feature matching, face detection. Gesture recognition. Weka toolkit.

  • Coursera courses audited in deep learning, neural networks, classical machine learning, classical AI, Udacity ADAS

  • Quantitative analysis of image quality and sensor performance; construction, simulation of sensor and camera models, signal-to-noise, dynamic range, color quality; closed-form and Monte-Carlo simulations

  • 3D image processing of various types, stereo imaging, wide dynamic range imaging, super-resolution

Deep Learning, Machine Learning Software

• • TensorFlow, TensorFlow Lite, TensorFlow Mobile, TensorFlow JS

  • Keras, Python

  • Matlab

  • Berkeley Caffe

  • NVIDIA CUDA, cuDNN, BLAS

  • OpenCV, OpenGL, OpenMP

Windows Software Development

• • Microsoft Visual Studio, MFC, Windows SDK, ActiveX, COM, ODBC, C#

  • Visual Basic, VBScript

  • Direct3D, DirectShow basics

Mobile App Development

• • 3 years of Android app development

  • Android Studio

Linux Development

• • Linux, gcc, virtual machines, VMware

  • Git, SVN, ClearCase, CVS, RCS, ClearCase

  • GitHub, BitBucket, Trello, Slack, continuous integration

Embedded Software Development

• • USB 2.0, USB 3.0 software and hardware design, USB Video Class

  • Cypress embedded development, Cypress FX3 firmware, Keil

  • ARM, ARM NEON, x86, 8080, Z80, 6811, 8051 assembly

  • ARC, ARC MetaWare;Texas Instruments Code Composer Studio

  • Familiar with CEVA DSP

Full Stack Web Development essentials

• • JavaScript

  • Angular, TypeScript

  • MEAN stackl Node.js, NPM, express.js, passport.js

  • MongoDb, mongoose.js; SQL

  • SSI

  • Bootstrap

  • WebRTC

  • Socket.io, yarn, Rollup, Webpack

  • Firebase

  • Redis

  • Legacy (CGI)

  • Wordpress

Cloud Computing

• • AWS Lambda, LightSail, Route 53

  • Google Cloud Platform (GCP)

  • DigitalOcean droplets, Kubernetes

  • Nginx, load balancers

  • Heroku, now.sh

  • Amazon Alexa Skills

Robotics and Self-driving/ADAS essentials

• • ROS, ROS v2

  • ADAS fundamentals (course)

  • SLAM, navigation, particle filter, Kalman filter 

  • Raspberry Pi, Arduino, TurtleBot 3

  • PCB design and layout, OrCAD, PADS, DDR layout

  • VEX robotics - coached middle-school team, team ranked 12th in 2017 “world” competition’s division

  • Matlab, SolidWorks, AutoCAD, 3D printing

ASIC Hardware

• • Cadence Encounter, physical implementation, taped out multiple imaging sensor ASICs

  • Cadence CAD suite and its administration

  • Synopsys CAD suite and its administration, Design Compiler, PrimeTime, PrimePower, Debussy

  • Analog/mixed signal simulation, layout essentials - Cadence Virtuoso, Analog Artist

  • Aldec ActiveHDL

Management

• • Project management, Cadence Management Corp.

  • Methodologies and legal issues for hiring

Education

• • Harvard Business School Executive Training

  • PhD in Computer Science, USC (2002) [Dissertation]

  • MS in Computer Science, USC (1999)

  • Bachelors Cum Laude in Computer Engineering (1995). Moscow (Russia) State Technical University of Radio Engineering, Electronics and Automation (MIREA), 1989-1995.

Media

• • Techo-On - [ISSCC] Samsung's CMOS Sensor Takes Range, RGB Images at Same Time

  • Tech Crunch - New Samsung Sensor Captures Both Light And Depth Data

  • MagnaChip press release, 

  • MagnaChip Opens Pasadena Research Center

  • People in the News

  • Reuters - R&D Leader Joins MagnaChip as VP of SoC Engineering

  • EETimes.com - MagnaChip beefs up U.S.-based R&D

  • Samsung NPU-related press releases

  • Samsung Introduces its First 5G-Integrated Mobile Processor, the Exynos 980

  • Samsung Brings On-device AI Processing for Premium Mobile Devices with Exynos 9 Series 9820 Processor

  • [Interview] How Samsung Developed the Galaxy S10’s Share-Friendly, AI-Powered Camera

  • How the Exynos 9 Series 9820 is Ushering in a New Era of Mobile Experiences

  • Samsung’s Exynos Auto V9 to Power Next-generation Platform for Audi’s In-vehicle Infotainment System

  • The Exynos 9 Series 9820: Intelligence from Within

Status

• • US citizen

Patents and Publications

• • 70+ granted patents, see list here.

• 20 publications as of 10/2019, see list here.